Kas nepareizi ar manu SPI paziņojumā?

[Leblanc]

Es tikai gribu darīt zināmu kliedziens APK virs SPI bet ne staigāt, piemēram, sagaidāms.var kāds man palīdzēt pamatus.

paldies
bibliotēkas IEEE;
izmantot IEEE.STD_LOGIC_1164.ALL;
izmantot IEEE.STD_LOGIC_ARITH.ALL;
izmantot IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment šādas bibliotēkas deklarāciju, ja instantiating
---- Jebkuru Xilinx primitīvas, ar šo kodu.
- Bibliotēka UNISIM;
- Izmantot UNISIM.VComponents.all;

vienība sinusa ir

Ports (CLK: ar STD_LOGIC;
clk2_p: no std_logic;
SPI_MOSI: no std_logic;
SPI_SS_B: no std_logic;
AMP_CS: no std_logic;
AD_CONV: no std_logic;
SF_CEO: no std_logic;
FPGA_INIT_B: no std_logic;
- Imput_word_t: no std_logic;
DAC_CS: no std_logic;
SPI_SCK: no std_logic;
SPI_MISO: ar std_logic;
slodze: no STD_LOGIC
);

beigās sinusa;

arhitektūras Uzvedības un sinus_574mhz ir

signāls shift_reg: std_logic_vector (11 downto 0): = (pārējie => '0 ');
signāls shift_reg1: std_logic: = '0 ';
signāls ZL: std_logic_vector (5 downto 0): = (pārējie => '0 ');

signāls sinuss: std_logic_vector (11 downto 0): = (pārējie => '0 ');
signāls apstāties: std_logic: = '0 ';
signāls temperatūra: std_logic_vector (23 downto 0): = (pārējie => '0 ');
pastāvīga ZERO: std_logic_vector (23 downto 0): = "000000000000000000000000";
signāls CLK2: std_logic: = '0 ';
signāls CLK3: std_logic: = '0 ';
signāls serial_data: std_logic: = '0 ';komponents sinusa
osta (
CLK: IN std_logic;
Sine: OUT std_logic_VECTOR (11 downto 0));
beigu komponents;

sākt
- Imput_word_t <= clk2;

- Adress <= "1111";
- Komanda <= "0011";
- SPI_SCK <= clk3;
SPI_SS_B <= "1";
AMP_CS <= "1";
AD_CONV <= '0 ';
SF_CEO <= "1";
FPGA_INIT_B <= "1";
- Imput_word <= komanda & adresi un sine un "XXXX";
clk2_p <= clk2;

bloc_1: sinusa
Ostas karte (
CLK => CLK,
Sine => obligāts);

process (clk2)
sākt
ja (clk2'event un clk2 = '0 '), tad
SPI_SCK <= clk3;
ja pārtraucat = "1", tad
SPI_SCK <= '0 ';
beidzas, ja;
beidzas, ja;
gala procesa;

-------------------------------------------------- ---------------------------

process (clk3, clk2)
sākt
ja clk2'event un clk2 = "1", tad
ja clk3 = "0", tad
ZL <= ZL 1, - komanda (4)
beidzas, ja;
beidzas, ja;
gala procesa;

process (clk3, clk2)
sākt
ja clk2'event un clk2 = "1", tad
ja clk3 = "0", tad
lieta ZL ir
kad "000000" =>
DAC_CS <= '0 ';
pārtraukt <= '0 ';
SPI_MOSI <= '0 '- dati (23);
kad "000001" =>
SPI_MOSI <= '0 '- dati (23);
kad "000010" =>
SPI_MOSI <= "1" - dati (23);
kad "000011" =>
SPI_MOSI <= "1" - dati (23);
kad "000100" =>
SPI_MOSI <= "1" - dati (23);
kad "000101" =>
SPI_MOSI <= "1" - dati (23);
kad "000110" =>
SPI_MOSI <= "1" - dati (23);
kad "000111" =>
SPI_MOSI <= "1" - dati (23);
kad "001000" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001001" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001010" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001011" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001100" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001101" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001110" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "001111" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "010000" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "010001" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "010010" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "010011" =>
SPI_MOSI <= shift_reg (11) - dati (23);
kad "010100" =>
SPI_MOSI <= 'X', - dati (23);
kad "010101" =>
SPI_MOSI <= 'X', - dati (23);
kad "010110" =>
SPI_MOSI <= 'X', - dati (23);
kad "010111" =>
SPI_MOSI <= 'X', - dati (23);

kad citi => - DAC_CS <= "1" - command_o <= 'X';
beigās lietā;

Ja ZL = "011000", tad
DAC_CS <= "1";
pārtraukt <= "1";

beidzas, ja;
beidzas, ja;
beidzas, ja;
gala procesa;

process (clk2)
sākt
ja rising_edge (clk2), tad
temp <= temp (22 downto 0) & SPI_MISO;
shift_reg1 <= temp (23);
beidzas, ja;
gala procesa;

-------------------------------------------------- ------------------------------------------

process (CLK), ir
mainīgais var_zustand_vektor: std_logic_vector (1 downto 0): = "00";
mainīgais var_zaehler_vektor: vesels skaitlis diapazonā līdz 249 0: = 0;

sāktja (CLK'event UN CLK = "1"), tad

CASE var_zustand_vektor ir
kad "00" =>
ja var_zaehler_vektor = 124, tad
var_zustand_vektor: = "01";
vēl
var_zaehler_vektor: = var_zaehler_vektor 1;
CLK2 <= "1";
beidzas, ja;
kad "01" =>
ja var_zaehler_vektor = 249, tad
var_zustand_vektor: = "00";
var_zaehler_vektor: = 0;
vēl
var_zaehler_vektor: = var_zaehler_vektor 1;
CLK2 <= '0 ';
beidzas, ja;
kad citi =>
var_zustand_vektor: = "00";
Beigās lieta;

beidzas, ja;
beigās procesu;

process (CLK2) ir
sākt
ja (CLK2'event UN CLK2 = "1"), tad
ja (clk3 = "0"), tad
clk3 <= "1";
vēl
clk3 <= '0 ';
beidzas, ja;
beidzas, ja;
beigās procesu;-------------------------------------------------- -------------------------process (clk2)
sākt
ja rising_edge (clk2), tad
- Slodze <= shift_reg (11);
shift_reg <= obligāts;
slodze <= shift_reg (11);
shift_reg (11 downto 1) <= shift_reg (10 downto 0);
beidzas, ja;
gala procesa;beigās Uzvedības;