[jautājums] Debug ieejas līmenī simulācijas erro par Altera?

[etrobin]

Cienījamie visiem,

Kad es palaist ieejas līmenī simulācija, es atklāju vienu kļūda rodas, bet tas pāriet, kad RTL simulācijas!Kā es varu izsekot kļūdu, netlist?Un kā es varu zināt uzvedību Altera apex20ke_lcell?Kas es norādīju, ir "regout" nepareizs, un CLK darba normālu ..........Thakn jums par atbildi!

<img src="http://www.edaboard.com/images/smiles/icon_biggrin.gif" alt="Loti laimīgs" border="0" />========================================
netlist ko rada qu (at) rtus uz Modelsim, ierīce ir APEX20KE
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apex20ke_lcell \ u_my_design | u_my_sub_design | u_test | X1_1_ (
/ / Vienādojums (s):
/ / \ U_my_design | u_my_sub_design | u_test | X1 [1] = \ u_my_design | u_my_sub_design | u_test | GO0_0 $ \ u_my_design | u_my_sub_design | u_test | GINFF [1] $ (\ u_my_design | u_my_sub_design | u_test | GO7_1)

. Dataa (\ u_my_design | u_my_sub_design | u_test | GO7_1)
. Datab (\ u_my_design | u_my_sub_design | u_test | GO0_0)
. Datac (\ u_my_design1 | u_my_sub_design1 | u_oo)
. Datad (\ u_my_design | u_my_sub_design | u_test | GINFF [1]),
. CIN (GND),
. Cascin (VCC)
. CLK (GND),
. Aclr (GND),
. ENA (VCC)
. Sclr (GND),
. Sload (GND),
. Devclrn (devclrn)
. Devpor (devpor)
. Combout (\ u_my_design | u_my_sub_design | u_test | X1 [1]),
. Regout ()
. Tiesas ()
. Cascout ());
/ / Synopsys translate_off
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_ =. operation_mode "normālu";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_ =. packed_mode "nepatiesu";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_. lut_mask = "39C6";
defparam \ u_my_design | u_my_sub_design | u_test | X1_1_ =. output_mode "comb_only";
/ / Synopsys translate_on

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