Vai šis bist vektora tiesības

H

HolySaint

Guest
Quote:

/ /

/ / Verilog formātā testa modeļiem, ko ražo v8.2005_5.10 MBISTArchitect

/ / Faila nosaukums: soc_tb_all.v.0.vec

/ / Idstamp:

/ / Datums: Wed novembris 19 10:39:12 2008

/ /

/ / Formāts kuģa borts vektora:

/ / PI_bits PO_bits MASK_bits Increment_bit Timeplate_bits (2) PatType_bits (3)

/ / VecType_bits (4)

/ / Increment_bit - norāda, kad pieauguma modelis skaits

/ / Timeplate_bits - kodē timeplate numurs, lai izmantotu

/ / PatType_bits - kodē modeli tips

/ / VecType_bits - kodē vektora veids/ / Bist testa bloka/ / Pattern 0 Cycle 0 Laikspiedols 0 ns

/ / Core Pattern: / ram_ctrl

/ / Cycle 0 Laikspiedols 0 ns

000000000000001000000XXXXXXXXXXXXXXXXXXXXXXXXXXXX0000000000000000000000000000Z010100000

/ / Core Pattern: / ram_ctrl

/ / Pattern 1 cikls 1 Laikspiedols 100 ns

/ / / Ram_ctrl - sākums viļņu formu ram_ctrl

000000000000001100000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000001100101011

/ / / Ram_ctrl - atiestatīšana Reģistri

000000000000000100000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000100101011

000000000000000101000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000100101011

000000000000000001101110000000011000000

0000000000000011010000XXXXXXXXXXXXXXXXXXXXXXXXX0X10000000000000000000000000100100101011

0001010000

0000000000000011010000XXXXXXXXXXXXXXXXXXXXXXXXX1X10000000000000000000000000100100101011

/ / Core Pattern: / rom_ctrl

/ / Pattern 2 Cycle 6 Laikspiedols 600 ns

000000000000001000000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000001010100000

/ / Core Pattern: / rom_ctrl

/ / Pattern 3 Cycle 7 Laikspiedols 700 ns

/ / / Rom_ctrl - sākums viļņu formu rom_ctrl

000000000000001100000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000001100101011

/ / / Rom_ctrl - atiestatīšana Reģistri

000000000000000100000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000100101011

000000000000000100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000100101011

000000000000000000101010000110011000000

/ / Cikls 10 Laikspiedols 1000 ns

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXX0X00000000000000000000000000100100101011

0001010000

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXX1X00000000000000000000000000100100101011

/ / Core Pattern: / rom_ud_cos512

/ / Pattern 4 Cycle 12 Laikspiedols 1200 ns

000000000000001000000XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000001010100000

/ / Core Pattern: / rom_ud_cos512

/ / Pattern 5 Cycle 13 Laikspiedols 1300 ns

/ / / Rom_ud_cos512 - sākums rom_ctrl_rom_ud_cos512_block_0 viļņu formu

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000001110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

/ / Cikls 20 Laikspiedols 2700 ns

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

/ / Cikls 30 Laikspiedols 4700 ns

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

/ / Cikls 40 Laikspiedols 6700 ns

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011

000000000000001100100XXXXXXXXXXXXXXXXXXXXXXXXXXXX00000000000000000000000000000110101011
 
Es domāju, ka tas ir nepareizi
kad es sim ar to,
fail_h signālu rāda man rslt ir nepareizi
bet kā es varu gen tiesības tb un ventor?
i izmantot mbistachitect

 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top