A
Augusts
Guest
Kā rakstīt verilog kodu FPGA saņemt ieguldījumu no datora tastatūras caur RS-232
Vai tas ir labi?
modulis serialfun (clk, RxD, TxD, GPout, GPin);
input CLK;
input RxD;
produkcija TxD;
izlaide [7:0] GPout;
ievade [7:0] GPin;
////////////////////////////////////////////////// /
stieple RxD_data_ready; stieple [7:0] RxD_data;
async_receiver deserializer (. clk (clk),. RxD (RxD),. RxD_data_ready (RxD_data_ready),. RxD_data (RxD_data));
reg [7:0] GPout;
vienmēr @ (posedge clk) if (RxD_data_ready) GPout <= RxD_data;
////////////////////////////////////////////////// /
async_transmitter serializēšanas (. clk (clk),. TxD (TxD),. TxD_start (RxD_data_ready),. TxD_data (GPin));
endmodule
Vai tas ir labi?
modulis serialfun (clk, RxD, TxD, GPout, GPin);
input CLK;
input RxD;
produkcija TxD;
izlaide [7:0] GPout;
ievade [7:0] GPin;
////////////////////////////////////////////////// /
stieple RxD_data_ready; stieple [7:0] RxD_data;
async_receiver deserializer (. clk (clk),. RxD (RxD),. RxD_data_ready (RxD_data_ready),. RxD_data (RxD_data));
reg [7:0] GPout;
vienmēr @ (posedge clk) if (RxD_data_ready) GPout <= RxD_data;
////////////////////////////////////////////////// /
async_transmitter serializēšanas (. clk (clk),. TxD (TxD),. TxD_start (RxD_data_ready),. TxD_data (GPin));
endmodule