Palīdziet man es esmu jauns techie par FPGA

R

ramesh441

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Hello Sir,

Es esmu jauns techie strādā pie SPARTEN 3E

No neto es atbraucu, lai zinātu, kā dump kods <4bits ievadi un pārbaudīt izejas <= 8bit

bet es aprunāt izprast to, kā piešķirt ieguldījumiem, kas kodu ņemot> 4bits
un pārbaudes rezultātu> 8bit

var jebkurā man palīdzēt

Paldies
Ramesh

 
&lt;a href="http://www.komputerswiat.pl/poradniki/programy/windows-7/2010/08/testujemy-szybkosc-dyskow-w-windows-7.aspx"&gt; &lt;img align="left" src="http://www.komputerswiat.pl/media/2010/240/1361854/Win7test-ZAJ.jpg" /&gt;&lt;/a&gt; Pokażemy wam jak sprawdzić prędkość odczytu i zapisu danych na dysku twardym. Wystarczy prosta komenda aby przetestować twardziela.&lt;img width='1' height='1' src='http://rss.feedsportal.com/c/32559/f/491281/s/d301793/mf.gif' border='0'/&gt;&lt;br/&gt;&lt;br/&gt;&lt;a href="http://da.feedsportal.com/r/78868891331/u/0/f/491281/c/32559/s/221255571/a2.htm"&gt;&lt;img src="http://da.feedsportal.com/r/78868891331/u/0/f/491281/c/32559/s/221255571/a2.img" border="0"/&gt;&lt;/a&gt;

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Hello Ramesh441,
Kādā valodā ur rakstiski ur programma VHDl r Verilog, Kāda ir programmu ur rakstīt, būs u post ur kods šeit, tad es varētu viegli palīdzēt u

Sveicieni
Kanimozhi.M

 
K, tad Post Ur kods, Do u zināt, kā strādāt Xilinx, Kura versija XIlinx UR izmantojot, būs u post ur kods šeitSveicieni
Kanimozhi.M

 
Es strādā pie xilix ISE webpack UN Spartan 3E KIT
Es vēlos zināt, kā 16 bitu ievade ir izturējis testē uz Spartas 3e komplektu ti, kad būs 16 ievade 4 slēdži un atpūtas?

, kur būs 16 izlaidē ir redzams tikai 8 ir dots LEDpašlaik IAM nav kods
I HAV ideju, kas pieprasa šosPaldies
Ramesh

 
jā Ramesh, U var nodot inputin pati programma, un izmantojot mux in ur kods un veikt pasākumus, kas izlaide LED, Ja u ir kods u var ievietot šeit, i palīdzēs u.

Sveicieni
Kanimozhi.M

 
Hello sir tas ir mans kods

Es gribu, lai dotu izejvielas
kur Spartas 3e komplektu es varu dot izejvielas
un kur es varu atrast outputs
################################################## ################modulis RCA (p, a, b);
produkcija [15:0] P;
inout [7:0] a;
inout [7:0] b;

stieple [7:0] C0, C1, C2, C3, C4, C5, C6, C7, s0, s1, s2, s3, S4, S5, S6, S7;
/ / stage0
singlecell st00 (. s0 (p [0]),. C0 (C0 [0]),. b (b [0]),. a (a [0]),. grēks (1'b0),. CIN ( 1'b0));
singlecell st01 (. s0 (s0 [1]),. C0 (C0 [1]),. b (b [0]),. a (a [1]),. grēks (1'b0),. CIN ( C0 [0]));
singlecell st02 (. s0 (s0 [2]),. C0 (C0 [2]),. b (b [0]),. a (a [2]),. grēks (1'b0),. CIN ( C0 [1]));
singlecell st03 (. s0 (s0 [3]),. C0 (C0 [3]),. b (b [0]),. a (a [3]),. grēks (1'b0),. CIN ( C0 [2]));

singlecell st04 (. s0 (s0 [4]),. C0 (C0 [4]),. b (b [0]),. a (a [4]),. grēks (1'b0),. CIN ( C0 [3]));
singlecell st05 (. s0 (s0 [5]),. C0 (C0 [5]),. b (b [0]),. a (a [5]),. grēks (1'b0),. CIN ( C0 [4]));
singlecell st06 (. s0 (s0 [6]),. C0 (C0 [6]),. b (b [0]),. a (a [6]),. grēks (1'b0),. CIN ( C0 [5]));
singlecell st07 (. s0 (s0 [7]),. C0 (C0 [7]),. b (b [0]),. a (a [7]),. grēks (1'b0),. CIN ( C0 [6]));
/ / stage1
singlecell st10 (. s0 (p [1]),. C0 (c1 [0]),. b (b [1]),. a (a [0]),. grēks (s0 [1]),. CIN (1'b0));
singlecell st11 (. s0 (s1 [1]),. C0 (c1 [1]),. b (b [1]),. a (a [1]),. grēks (s0 [2]),. CIN (c1 [0]));
singlecell st12 (. s0 (s1 [2]),. C0 (c1 [2]),. b (b [1]),. a (a [2]),. grēks (s0 [3]),. CIN (c1 [1]));
singlecell st13 (. s0 (s1 [3]),. C0 (c1 [3]),. b (b [1]),. a (a [3]),. grēks (s0 [4]),. CIN (c1 [2]));

singlecell st14 (. s0 (S1 [4]),. C0 (c1 [4]),. b (b [1]),. a (a [4]),. grēks (s0 [5]),. CIN (c1 [3]));
singlecell st15 (. s0 (s1 [5]),. C0 (c1 [5]),. b (b [1]),. a (a [5]),. grēks (s0 [6]),. CIN (c1 [4]));
singlecell st16 (. s0 (s1 [6]),. C0 (c1 [6]),. b (b [1]),. a (a [6]),. grēks (s0 [7]),. CIN (c1 [5]));
singlecell st17 (. s0 (s1 [7]),. C0 (c1 [7]),. b (b [1]),. a (a [7]),. grēks (C0 [7]),. CIN (c1 [6]));
/ / stage2
singlecell st20 (. s0 (p [2]),. C0 (c2 [0]),. b (b [2]),. a (a [0]),. grēks (s1 [1]),. CIN (1'b0));
singlecell st21 (. s0 (S2 [1]),. C0 (c2 [1]),. b (b [2]),. a (a [1]),. grēks (s1 [2]),. CIN (c2 [0]));
singlecell st22 (. s0 (S2 [2]),. C0 (c2 [2]),. b (b [2]),. a (a [2]),. grēks (s1 [3]),. CIN (C2) [1]);
singlecell st23 (. s0 (S2 [3]),. C0 (c2 [3]),. b (b [2]),. a (a [3]),. grēks (S1 [4]),. CIN (c2 [2]));
singlecell st24 (. s0 (S2 [4]),. C0 (C2 [4]),. b (b [2]),. a (a [4]),. grēks (s1 [5]),. CIN (C2) [3]);
singlecell st25 (. s0 (S2 [5]),. C0 (c2 [5]),. b (b [2]),. a (a [5]),. grēks (s1 [6]),. CIN (C2 [4]));
singlecell st26 (. s0 (S2 [6]),. C0 (c2 [6]),. b (b [2]),. a (a [6]),. grēks (s1 [7]),. CIN (c2 [5]));
singlecell st27 (. s0 (S2 [7]),. C0 (C2 [7]),. b (b [2]),. a (a [7]),. grēks (c1 [7]),. CIN (c2 [6]));
/ / stage3
singlecell st30 (. s0 (p [3]),. C0 (C3 [0]),. b (b [3]),. a (a [0]),. grēks (S2 [1]),. CIN (1'b0));
singlecell st31 (. s0 (S3 [1]),. C0 (C3 [1]),. b (b [3]),. a (a [1]),. grēks (S2 [2]),. CIN (C3 [0]));
singlecell st32 (. s0 (S3 [2]),. C0 (C3 [2]),. b (b [3]),. a (a [2]),. grēks (S2 [3]),. CIN (C3) [1]);
singlecell st33 (. s0 (S3 [3]),. C0 (C3 [3]),. b (b [3]),. a (a [3]),. grēks (S2 [4]),. CIN (C3 [2]));
singlecell st34 (. s0 (S3 [4]),. C0 (C3 [4]),. b (b [3]),. a (a [4]),. grēks (S2 [5]),. CIN (C3) [3]);
singlecell st35 (. s0 (S3 [5]),. C0 (C3 [5]),. b (b [3]),. a (a [5]),. grēks (S2 [6]),. CIN (C3 [4]));
singlecell st36 (. s0 (S3 [6]),. C0 (C3 [6]),. b (b [3]),. a (a [6]),. grēks (S2 [7]),. CIN (C3 [5]));
singlecell st37 (. s0 (S3 [7]),. C0 (C3 [7]),. b (b [3]),. a (a [7]),. grēks (C2 [7]),. CIN (C3 [6]));

/ / stage4

singlecell st40 (. s0 (p [4]),. C0 (C4 [0]),. b (b [4]),. a (a [0]),. grēks (S3 [1]),. CIN (1'b0));
singlecell st41 (. s0 (S4 [1]),. C0 (C4 [1]),. b (b [4]),. a (a [1]),. grēks (S3 [2]),. CIN (C4 [0]));
singlecell st42 (. s0 (S4 [2]),. C0 (C4 [2]),. b (b [4]),. a (a [2]),. grēks (S3 [3]),. CIN (C4) [1]);
singlecell st43 (. s0 (S4 [3]),. C0 (C4 [3]),. b (b [4]),. a (a [3]),. grēks (S3 [4]),. CIN (C4 [2]));
singlecell st44 (. s0 (S4 [4]),. C0 (C4 [4]),. b (b [4]),. a (a [4]),. grēks (S3 [5]),. CIN (C4) [3]);
singlecell st45 (. s0 (S4 [5]),. C0 (C4 [5]),. b (b [4]),. a (a [5]),. grēks (S3 [6]),. CIN (C4 [4]));
singlecell st46 (. s0 (S4 [6]),. C0 (C4 [6]),. b (b [4]),. a (a [6]),. grēks (S3 [7]),. CIN (C4 [5]));
singlecell st47 (. s0 (S4 [7]),. C0 (C4 [7]),. b (b [4]),. a (a [7]),. grēks (C3 [7]),. CIN (C4 [6]));

/ / stadiju 5

singlecell st50 (. s0 (p [5]),. C0 (C5 [0]),. b (b [5]),. a (a [0]),. grēks (S4 [1]),. CIN (1'b0));
singlecell st51 (. s0 (S5 [1]),. C0 (C5 [1]),. b (b [5]),. a (a [1]),. grēks (S4 [2]),. CIN (C5 [0]));
singlecell ST52 (. s0 (S5 [2]),. C0 (C5 [2]),. b (b [5]),. a (a [2]),. grēks (S4 [3]),. CIN (C5) [1]);
singlecell st53 (. s0 (S5 [3]),. C0 (C5 [3]),. b (b [5]),. a (a [3]),. grēks (S4 [4]),. CIN (C5 [2]));
singlecell st54 (. s0 (S5 [4]),. C0 (C5 [4]),. b (b [5]),. a (a [4]),. grēks (S4 [5]),. CIN (C5) [3]);
singlecell st55 (. s0 (S5 [5]),. C0 (C5 [5]),. b (b [5]),. a (a [5]),. grēks (S4 [6]),. CIN (C5 [4]));
singlecell st56 (. s0 (S5 [6]),. C0 (C5 [6]),. b (b [5]),. a (a [6]),. grēks (S4 [7]),. CIN (C5 [5]));
singlecell st57 (. s0 (S5 [7]),. C0 (C5 [7]),. b (b [5]),. a (a [7]),. grēks (C4 [7]),. CIN (C5 [6]));

/ / posmā 6

singlecell st60 (. s0 (p [6]),. C0 (C6 [0]),. b (b [6]),. a (a [0]),. grēks (S5 [1]),. CIN (1'b0));
singlecell st61 (. s0 (S6 [1]),. C0 (C6 [1]),. b (b [6]),. a (a [1]),. grēks (S5 [2]),. CIN (C6 [0]));
singlecell st62 (. s0 (S6 [2]),. C0 (C6 [2]),. b (b [6]),. a (a [2]),. grēks (S5 [3]),. CIN (C6) [1]);
singlecell st63 (. s0 (S6 [3]),. C0 (C6 [3]),. b (b [6]),. a (a [3]),. grēks (S5 [4]),. CIN (C6 [2]));
singlecell st64 (. s0 (S6 [4]),. C0 (C6 [4]),. b (b [6]),. a (a [4]),. grēks (S5 [5]),. CIN (C6 [3]));
singlecell st65 (. s0 (S6 [5]),. C0 (C6 [5]),. b (b [6]),. a (a [5]),. grēks (S5 [6]),. CIN (C6 [4]));
singlecell st66 (. s0 (S6 [6]),. C0 (C6 [6]),. b (b [6]),. a (a [6]),. grēks (S5 [7]),. CIN (C6 [5]));
singlecell st67 (. s0 (S6 [7]),. C0 (C6 [7]),. b (b [6]),. a (a [7]),. grēks (C5 [7]),. CIN (C6 [6]));

/ / stadiju 7

singlecell st70 (. s0 (p [7]),. C0 (C7 [0]),. b (b [7]),. a (a [0]),. grēks (S6 [1]),. CIN (1'b0));
singlecell st71 (. s0 (p [8]),. C0 (C7 [1]),. b (b [7]),. a (a [1]),. grēks (S6 [2]),. CIN (C7 [0]));
singlecell st72 (. s0 (p [9]),. C0 (C7 [2]),. b (b [7]),. a (a [2]),. grēks (S6 [3]),. CIN (C7) [1]);
singlecell st73 (. s0 (p [10]),. C0 (C7 [3]),. b (b [7]),. a (a [3]),. grēks (S6 [4]),. CIN (C7 [2]));
singlecell st74 (. s0 (p [11]),. C0 (C7 [4]),. b (b [7]),. a (a [4]),. grēks (S6 [5]),. CIN (C7) [3]);
singlecell st75 (. s0 (p [12]),. C0 (C7 [5]),. b (b [7]),. a (a [5]),. grēks (S6 [6]),. CIN (C7 [4]));
singlecell st76 (. s0 (p [13]),. C0 (C7 [6]),. b (b [7]),. a (a [6]),. grēks (S6 [7]),. CIN (C7 [5]));
singlecell st77 (. s0 (p [14]),. C0 (p [15]),. b (b [7]),. a (a [7]),. grēks (C6 [7]),. CIN (C7 [6]));
/ / piešķir p [15:0] = (C7 [7], S7 [7:0], S6 [0], S5 [0], s4 [0], s3 [0], s2 [0], s1 [ 0], s0 [0]);
endmodule
modulis singlecell (s0, C0, b, a, grēks, CIN);
izlaides s0;
inout a;
izlaides C0;
inout b;
ievade grēks;
/ / Ievades a;
/ / Ievades b;
ievade CIN;
stieples temperatūra;
un A1 (temp, a, b);
add_32 B1 (
. s (s0),. c (C0),. a (grēks),. b (temp),. CIN (CIN));endmodule
modulis add_32 (s, c, a, b, CIN);
izlaides s;
izlaides c;
ievadi a;
ievade b;
ievade CIN;
stieple x, y, z;
xor (s, a, b, CIN);
un a1 (x, a, b);
un A2 (y, b, CIN);
un A3 (z, CIN, a);
vai (c, x, y, z);

endmodule
################################################## #########################

Paldies
Ramesh

 
Hello Ramesh,

Jūsu jautājums nav tik skaidra.Bet viena lieta, ko es var ieteikt Jums ir jābūt skaidrībā par šo problēmu.Tad sākt darbu pie tā, soli pa solim.

Jūs esat
1.xilix ISE webpack
2.Spartan 3E KIT
3.Jūs esat kods (16 izejvielām un 16 rezultātiem).

Pirmās saprast plūsmas, kā konfigurēt kodu FPGA kuģa.

1.Izstrādāt UCF (lietotājs ierobežojums) failu.
2.Attiecībā UCF failu minēt, kādu informāciju ir saistīta ar kuriem pin no FPGA.
3.Un arī pieminēt, kas rezultāts ir saistīts ar LED ar kuģa.
4.LED LOCCATION informācija tiks sniegta ar FPGA kuģa atsauces rokasgrāmatu.

Tātad, mans ieteikums ir pirmais attīstīt UCF.

Sveicieni,
Sunil Budumuru
Last edited by sunilbudumuru 21 Apr 2009 14:09, edited 1 time kopā

 
Hello SirJums ir pareizi

I sintezētās mans kods
Tagad es vēlos dump to Spartan 3E kit

Es varētu darīt, bet tajā pašā laikā piešķirot ievade pins ir 16 izejvielām un par boardd mēs esam tikai 4 slēdžiKā es piešķirt citur pins

Lai gan pārbaudīt izejas ir tikai 8 rezultātā, kas atrodas uz kuģa, kā mēs varētu pārbaudīt produkcijas (16)Paldies
Ramesh

 
tikai atstāt citur tapas ievadparametrus

un

un tikai lietošanai 2 izejas vai vārtiem un veikt galīgo 8 outputs (vai)

Just izmantot tikai 8 rezultātus un atstāj pārējo.Nav problēmu ....

 
Paldies par Jūsu atbildi sir,Sir var, lūdzu pasakiet man pilnīgi, cik daudz izejvielu un, cik outputs būs tur ir Spartas 3e, un ja tās ir klāt
un par to, kā savienot tos

Patiesībā es zinu ļoti maz pamata s komplektu.

Thankyou
Ramesh

 
jūs varat lejupielādēt spartietis datu no Xilinx.Jūs varat atrast visu nepieciešamo info tur

 
Es izlasīju, bet tā dots par to, slēdži un visas stuff

Godātais kungs, ja vēlos, lai dotu 8 ievades laikā, uz Spartas 3e komplekts, kā varētu i

 
skatīt IO bufferes ar Spartas un pārbauda pin atrašanās vietu, ka IO buferiem.

Tagad ir UCF failu u minēt, kādu informāciju vai Output pin ir conected uz corresponsing ISP no Spartas.

Tā kā ucf izmantot LOC ....veida stuff.I did this sen atpakaļ.

 
Thank you so much for your Atbildēt

Es esmu es tring tādā veidā
Ceru, ka es sasniegta, to

Paldies,
Ramesh

 
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