AWGN kanāls modeli Verilog

[IEEE]

Mani interesē, vai kāds bija šis verilog.Man, lūdzu, C, C un Matlab redakcijas bat ieinteresēta iegūt ABL versiju.

 

[yakinlu]

I m vajag pārāk. Var u analizēt kodu šādi:

************************************************** *****************************/
/************************************************* ******************************
Modulis rada troksni, izmantojot downlink m-virknes.
X secība ir būvēts pēc primitīva polinoma
1 x (7) x (18).
Y secība ir būvēts pēc ploynomial
1 x (5) x (7) x (10) x (18).

x iniatialized ar x (0) = x (1) = x (2) ...= X (17) = 0,
rekursīvas definīcija
x (i 18) = x (i 7) x (i) modulo 2.

y ir iniatialized ar y (0) = y (1) = y (2) ...= Y (17) = 1.
rekursīvas definīcija
Y (I 18) = y (i 10) y (i 7) y (i 5) y (i) modulo 2.

Trokšņa izlaide ir z (i) = x (i) y (i) modulo 2.

************************************************** *****************************/

modulis GEN_NOISE (
/ / Ievades datu
Clk16,
Reset,
Node_sync,
Channel_noise,

/ / Izejas dati
Noise_data
) / * Sintēze syn_hier = "cietās" * /;input Clk16;
input Reset;
input Node_sync;
ievade [9:0] Channel_noise;

/ / Izejas dati
izlaide [9:0] Noise_data;

reg [9:0] Noise_data;
reg Noise_start;
reg [17:0] Xseq;
reg [17:0] Yseq;

stieple [1:0] Xshift;
stieple [2:0] Yshift;
stieple [1:0] Noise_out;
stieple [9:0] N_NOISE_ENG;

/ / Modulis sākuma.

//************************************************ ******************************
////////////////////////////////////////////////// //////////////////////////////
/ / Wait mezgls sinhronā signālu.

vienmēr @ (posedge Clk16 vai posedge Reset)
sākt
if (Reset == 1'b1)
Noise_start <= 1'b0;
citādi
if (Node_sync == 1'b1)
Noise_start <= 1'b1;
citur;
beigas

////////////////////////////////////////////////// //////////////////////////////
//************************************************ ******************************

//************************************************ ******************************
////////////////////////////////////////////////// //////////////////////////////
/ / Izveidot x un y secību.

uzdot Xshift = Xseq [7] Xseq [0];

vienmēr @ (posedge Clk16 vai posedge Reset)
sākt
if (Reset == 1'b1)
Xseq <= 18'b0;
citādi
if (Noise_start == 1'b1)
sākt
Xseq [16:0] <= Xseq [17:1];
Xseq [17] <= Xshift [0];
beigas
citur;
beigas

////////////////////////////////////////////////// //////////////////////////////

uzdot Yshift = Yseq [10] Yseq [7] Yseq [5] Yseq [0];

vienmēr @ (posedge Clk16 vai posedge Reset)
sākt
if (Reset == 1'b1)
Yseq <= 18'h3ffff;
citādi
if (Noise_start == 1'b1)
sākt
Yseq [16:0] <= Yseq [17:1];
Yseq [17] <= Yshift [0];
beigas
citur;
beigas

////////////////////////////////////////////////// //////////////////////////////
//************************************************ ******************************
/ / Izveidot trokšņu datiem.

uzdot Noise_out = Xseq [0] Yseq [0];

uzdot N_NOISE_ENG = (~ Channel_noise) 1;

vienmēr @ (posedge Clk16 vai posedge Reset)
sākt
if (Reset == 1'b1)
Noise_data <= 11'b0;
citādi
if (Noise_start == 1'b1)
if (Noise_out [0] == 1'b1)
Noise_data <= N_NOISE_ENG;
citādi
Noise_data <= Channel_noise;
citādi
;
beigas////////////////////////////////////////////////// //////////////////////////////

endmodule / / End GEN_NOISE